Programmable logic devices (PLDs) such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are integrated circuits (ICs) devices that include generic structures and logic blocks that can be configured to perform different functions. Some of these logic blocks include logic circuitry, registers, I/O blocks, memory blocks, digital signal processing (DSP) blocks, various configurable blocks, etc. These circuitry elements are programmable to perform any of a variety of tasks and functions.
A user may design an application on an IC device and configure the IC device to perform certain tasks and functions. Generally speaking, the user may use a software design tool, e.g., the assignee's QUARTUS® II software, to compile the circuit design to generate a configuration file that can be used to configure the actual IC device. Compiling the circuit design involves taking a design description, usually written in a hardware description language (HDL), synthesizing the design description to generate a netlist description of the design, placing and routing the design on a selected IC device, performing timing analysis, checking the design for design rule violations, etc. Generally speaking, the software design tool will perform any of a variety of these steps to generate a bitstream configuration file.
After the design is compiled, i.e., modeled and simulated, the actual IC device is configured with the design using the generated configuration file. Even though the compiled design is relatively free from errors, there are instances when the design will still fail during runtime if the circuit design did not follow specific design rules or timing processes. For instance, a circuit design that violates certain design rules may still be compiled even if the circuit designer chose to ignore those violations. However, when the design is implemented on the actual IC device, the affected blocks may fail during operation of the IC device.
Under these circumstances, it is difficult for the user tell if the failure is a hardware failure or a design failure. This makes it relatively harder to pinpoint the cause of the failure when there is no apparent hardware defect.